Silicon photonics exploiting silicon photonic integrated circuits (PICs) relates to the application of photonic systems which use silicon as an optical medium. The silicon is usually patterned with sub-micrometer precision, into photonic components and photonic integrated circuits which operate in the infrared, most commonly at the 1550 nm (1.55 μm) wavelength window used by most fiber optic telecommunication systems as it is the lowest attenuation region for singlemode silica optical fibers. In reality the silicon typically lies on top of a layer of silica in what by analogy with a similar construction in microelectronics for transistors is known as silicon on insulator (SOI).
Silicon photonic devices exploit existing semiconductor fabrication techniques, and because silicon is already used as the substrate for most integrated circuits, it is possible to create hybrid devices in which the optical and electronic components are integrated onto a single microchip. Consequently, silicon photonics is being actively researched by many electronics manufacturers as well as by academic research groups.
Accordingly, within SOI waveguides the high index contrast between silicon (nSI=3.47), the underlying silica (silicon dioxide, SiO2, nSILICA=1.6), and either air (nAIR=1) or silica cladding, does not allow light, at 1550 nm, to extend into the silicon oxide beyond a fraction of a micron. The use of a rib loaded waveguide structure on the top surface of a silicon chip guides the optical power in the plane of the silicon as the effective refractive index in the region with the rib is higher than the adjacent regions without the rib. The resulting SOI waveguide is tightly confined vertically and loosely confined laterally and due to the index contrast Δn˜57% SOI waveguides have a small mode field diameter (MFD≈0.3 μm).
In contrast singlemode fiber (SMF) with a germanium doped silica core with silica cladding or silica core with fluorine doped silica cladding have a low index contrast, Δn≈0.036%, such that the typical MFD≈10.4 μm. Accordingly, when a silicon photonic device is to be interfaced to SMF optical fiber then the ratio of mode area ratio between SOI and SMF is approximately 1:1000 (SOI˜0.09 μm2:SMF˜85 μm2). Accordingly, it is necessary to implement silicon-on-insulator-based adiabatic waveguide tapers with a high coupling efficiency and small footprint in order to couple into the silicon photonic integrated circuits from the SMF optical fiber or vice-versa.
Within the prior art linear and parabolic tapers have been described and implemented to provide such transitions onto and off of the silicon photonic integrated circuit. However, these tend to be high loss and absorb valuable die footprint such that it would be beneficial to provide SOI PIC designers with a taper geometry that offers lower insertion loss and smaller footprint than the prior art but maintains compatibility with standard manufacturing methodologies.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.